Source
HamiltonianCircuit/SimpleGraph
Target
Satisfiability
Motivation
This direct CNF encoding connects Hamiltonian Circuit to the SAT hub without passing through an optimization model. It is a canonical example of exposing a combinatorial witness through executable logical constraints.
Reference
Cook, S. A. “The Complexity of Theorem-Proving Procedures,” STOC 1971; Garey and Johnson, Computers and Intractability, 1979; Velev and Gao, “Efficient SAT Techniques for Absolute Encoding of Permutation Problems: Application to Hamiltonian Cycles,” SARA 2009. Velev and Gao's absolute encoding uses one predicate for each vertex-position pair and adjacency constraints excluding impossible consecutive vertices, matching the construction below. Cook's theorem supports the generic NP-to-CNF-SAT claim but does not state this position encoding.
Reduction Algorithm
Given G=(V,E), V={0,...,n-1}:
- If
n<3, output the fixed contradiction (z) AND (not z), matching the source model's explicit rejection of circuits with fewer than three vertices.
- Otherwise create Boolean variable
x[v,p] meaning vertex v occurs at cyclic position p, for all v,p in {0,...,n-1}.
- For every position
p, add one clause requiring some vertex at p, and pairwise clauses forbidding two vertices at p.
- For every vertex
v, add one clause requiring v in some position, and pairwise clauses forbidding v in two positions.
- For every cyclic successor pair
p,q=(p+1) mod n and every ordered pair (u,v) that is equal or is not an edge, add not x[u,p] OR not x[v,q].
- Extract the circuit by reading the unique true vertex at each position.
The first four clause families force a permutation of the vertices. The last family accepts exactly those permutations whose consecutive pairs, including the closing pair, are graph edges. Isolated or disconnected vertices therefore make the formula unsatisfiable whenever they prevent a circuit. Self-loops cannot supply a successor because equal consecutive vertices are explicitly forbidden, and parallel copies of an edge do not change whether the corresponding successor pair is allowed.
Size Overhead
Safe upper bounds, including the fixed small-instance contradiction:
| Target metric |
Formula |
num_vars |
num_vertices * num_vertices + 1 |
num_clauses |
2 * num_vertices + num_vertices * num_vertices * (num_vertices - 1) + num_vertices^3 + 2 |
num_literals |
4 * num_vertices^3 + 2 |
Validation Method
- Exhaust every simple graph through four vertices.
- Brute-force both vertex permutations and SAT feasibility and compare the results.
- Separately test the
n<3 contradiction and extraction of both circuit orientations.
Example
- Source YES instance: five-cycle
01,12,23,34,40 plus chord 02.
- Construction: create 25 variables
x[v,p] and the four uniqueness/adjacency clause families above. Representative forbidden-successor clause: because {0,3} is not an edge, every position p contains not x[0,p] OR not x[3,p+1].
- Target witness: set
x[0,0],x[1,1],x[2,2],x[3,3],x[4,4] true and all other variables false.
- Round trip: the assignment satisfies every clause and extracts cycle
0-1-2-3-4-0. Swapping positions of vertices 2 and 3 violates a successor clause, so the example detects missing adjacency constraints.
- Source NO instance: the five-vertex path
01,12,23,34. Its endpoint 0 has only one distinct neighbor, but any encoded cyclic permutation would give it two distinct consecutive neighbors. Thus every placement of 0 violates a forbidden-successor clause on one side, and the target CNF is unsatisfiable.
BibTeX
@inproceedings{Cook1971,
author = {Cook, Stephen A.},
title = {The Complexity of Theorem-Proving Procedures},
booktitle = {Proceedings of the Third Annual ACM Symposium on Theory of Computing},
pages = {151--158},
year = {1971},
doi = {10.1145/800157.805047}
}
@book{GareyJohnson1979,
author = {Garey, Michael R. and Johnson, David S.},
title = {Computers and Intractability: A Guide to the Theory of NP-Completeness},
publisher = {W. H. Freeman},
year = {1979}
}
@inproceedings{VelevGao2009,
author = {Velev, Miroslav N. and Gao, Ping},
title = {Efficient SAT Techniques for Absolute Encoding of Permutation Problems: Application to Hamiltonian Cycles},
booktitle = {Proceedings of the Eighth Symposium on Abstraction, Reformulation and Approximation},
pages = {159--166},
publisher = {AAAI Press},
year = {2009}
}
Source
HamiltonianCircuit/SimpleGraph
Target
Satisfiability
Motivation
This direct CNF encoding connects Hamiltonian Circuit to the SAT hub without passing through an optimization model. It is a canonical example of exposing a combinatorial witness through executable logical constraints.
Reference
Cook, S. A. “The Complexity of Theorem-Proving Procedures,” STOC 1971; Garey and Johnson, Computers and Intractability, 1979; Velev and Gao, “Efficient SAT Techniques for Absolute Encoding of Permutation Problems: Application to Hamiltonian Cycles,” SARA 2009. Velev and Gao's absolute encoding uses one predicate for each vertex-position pair and adjacency constraints excluding impossible consecutive vertices, matching the construction below. Cook's theorem supports the generic NP-to-CNF-SAT claim but does not state this position encoding.
Reduction Algorithm
Given
G=(V,E),V={0,...,n-1}:n<3, output the fixed contradiction(z) AND (not z), matching the source model's explicit rejection of circuits with fewer than three vertices.x[v,p]meaning vertexvoccurs at cyclic positionp, for allv,p in {0,...,n-1}.p, add one clause requiring some vertex atp, and pairwise clauses forbidding two vertices atp.v, add one clause requiringvin some position, and pairwise clauses forbiddingvin two positions.p,q=(p+1) mod nand every ordered pair(u,v)that is equal or is not an edge, addnot x[u,p] OR not x[v,q].The first four clause families force a permutation of the vertices. The last family accepts exactly those permutations whose consecutive pairs, including the closing pair, are graph edges. Isolated or disconnected vertices therefore make the formula unsatisfiable whenever they prevent a circuit. Self-loops cannot supply a successor because equal consecutive vertices are explicitly forbidden, and parallel copies of an edge do not change whether the corresponding successor pair is allowed.
Size Overhead
Safe upper bounds, including the fixed small-instance contradiction:
num_varsnum_vertices * num_vertices + 1num_clauses2 * num_vertices + num_vertices * num_vertices * (num_vertices - 1) + num_vertices^3 + 2num_literals4 * num_vertices^3 + 2Validation Method
n<3contradiction and extraction of both circuit orientations.Example
01,12,23,34,40plus chord02.x[v,p]and the four uniqueness/adjacency clause families above. Representative forbidden-successor clause: because{0,3}is not an edge, every positionpcontainsnot x[0,p] OR not x[3,p+1].x[0,0],x[1,1],x[2,2],x[3,3],x[4,4]true and all other variables false.0-1-2-3-4-0. Swapping positions of vertices 2 and 3 violates a successor clause, so the example detects missing adjacency constraints.01,12,23,34. Its endpoint 0 has only one distinct neighbor, but any encoded cyclic permutation would give it two distinct consecutive neighbors. Thus every placement of 0 violates a forbidden-successor clause on one side, and the target CNF is unsatisfiable.BibTeX