From 5d7d68d8f67809dea5407ac5b973f2565cf32aa3 Mon Sep 17 00:00:00 2001 From: anurag Date: Wed, 22 Jul 2026 13:24:06 -0600 Subject: [PATCH 1/2] add spare reg to status Signed-off-by: anurag --- src/mldebug/aie_status.py | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/src/mldebug/aie_status.py b/src/mldebug/aie_status.py index 91daa56..8e6a553 100644 --- a/src/mldebug/aie_status.py +++ b/src/mldebug/aie_status.py @@ -136,7 +136,7 @@ def _append_bd_status(self, mtype, registers): regdata = filtered_regdata self.results[mtype][table].append((rsearch, c, r, regdata)) - def append_status(self, mtype, rtype, regs, coalesce=False, _hex=True): + def append_status(self, mtype, rtype, regs, coalesce=False, _hex=True, simple=False): """ Get and append status for a module type to results. @@ -146,6 +146,7 @@ def append_status(self, mtype, rtype, regs, coalesce=False, _hex=True): regs: List or tuple of (register name, register address) pairs. coalesce: Save results on a per tile basis if True. _hex: Save register values as hex strings if True. + simple: Just print register values. hex or not """ extra_meta = "" if rtype not in self.results[mtype].keys(): @@ -159,7 +160,10 @@ def append_status(self, mtype, rtype, regs, coalesce=False, _hex=True): parsed_reg = self.aie_iface.parse_register(name, regdata) if _hex: regdata = hex(regdata) - self.results[mtype][rtype].append((name, c, r, regdata, extra_meta, parsed_reg)) + if not simple: + self.results[mtype][rtype].append((name, c, r, regdata, extra_meta, parsed_reg)) + else: + self.results[mtype][rtype].append(("",c, r, regdata)) else: regdata = [] for name, reg in regs: @@ -423,6 +427,12 @@ def update(self, tile_type=None, vaiml=False, advanced=False, debug_map_json=Non self._get_advanced_metrics(ttype, regmap, advanced) if ttype == self.aie_iface.MEM_TILE_T: self._get_advanced_metrics(ttype, self.aie_iface.Memory_tile_registers, advanced) + + extra_metrics = ["SPARE_REG"] + regmap = self.aie_iface.Memory_tile_registers + for rtype in extra_metrics: + regs = [(k, v) for k, v in regmap.items() if rtype in k] + self.append_status(ttype, rtype, regs, _hex=False, simple=True) # Shim Microcontroller if ttype == self.aie_iface.SHIM_TILE_T: regmap = self.aie_iface.Shim_tile_registers From 960fc56c740f88cf0d6af71da820064b3a8b37aa Mon Sep 17 00:00:00 2001 From: anurag Date: Wed, 22 Jul 2026 13:29:55 -0600 Subject: [PATCH 2/2] fix spacing Signed-off-by: anurag --- src/mldebug/aie_status.py | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/mldebug/aie_status.py b/src/mldebug/aie_status.py index 8e6a553..54ef77c 100644 --- a/src/mldebug/aie_status.py +++ b/src/mldebug/aie_status.py @@ -148,7 +148,6 @@ def append_status(self, mtype, rtype, regs, coalesce=False, _hex=True, simple=Fa _hex: Save register values as hex strings if True. simple: Just print register values. hex or not """ - extra_meta = "" if rtype not in self.results[mtype].keys(): self.results[mtype][rtype] = [] for c, r in self.get_debug_tiles(mtype, raw=True): @@ -161,9 +160,9 @@ def append_status(self, mtype, rtype, regs, coalesce=False, _hex=True, simple=Fa if _hex: regdata = hex(regdata) if not simple: - self.results[mtype][rtype].append((name, c, r, regdata, extra_meta, parsed_reg)) + self.results[mtype][rtype].append((name, c, r, regdata, "", parsed_reg)) else: - self.results[mtype][rtype].append(("",c, r, regdata)) + self.results[mtype][rtype].append(("" ,c, r, regdata)) else: regdata = [] for name, reg in regs: