eMMC and UART clock changes on AMD platforms - #290
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rajaganeshr
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Jul 28, 2026
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- cherrypicked high speed UART clock speed from integ_sp8 to dev-6.18
- enable 8-bit width for eMMC and increase drive strength to 8mA
Add uart-clk-source to the AST2700 SCU1 syscon node. UART defaults to UXCLK (supports up to 115200 baud). For high-speed UART (>115200), UART clock source must switch to HUXCLK. The uart-clk-source bitfield controls this per UARTx (LSB-first), so set it to <0xfff> for all instances. Tested: Verified on kenya. uart-clk-source is present under syscon1:syscon@14c02000 with value <0xff0>. Signed-off-by: Rajaganesh Rathinasabapathi <Rajaganesh.Rathinasabapathi@amd.com>
Configure the eMMC data bus and pin mux for eight-bit operation, and set its CLK, CMD, and data pins to 8 mA drive strength. Tested: Compiled successfully and verified on Arthur Signed-off-by: Rajaganesh Rathinasabapathi <Rajaganesh.Rathinasabapathi@amd.com> Co-authored-by: Cursor <cursoragent@cursor.com>
rajaganeshr
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modolaty
July 28, 2026 14:46
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