Increase emmc drive strength - #291
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This patch adds pinmux support for the AST2700, which includes two SoC configurations: - SoC0 closely resembles previous generations of ASPEED BMC SoCs, allowing the reuse of existing macros and callback functions. - SoC1, however, introduces a new logic for configuring pin functions. Therefore, new g7_set_mux and gpio_request_enable functions are implemented to properly configure the pinctrl registers using the pin_cfg table and to resolve GPIO request errors. The driver supports: - All 12 GPIO-capable pins in SoC0 - All 212 GPIO-capable pins in SoC1 Additionally, this patch introduces several pseudo-ball definitions for specific configuration purposes: - USB function selection - JTAG target selection - PCIe RC PERST configuration - SGMII PHY selection Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Change-Id: I5630dac8b73427f794d8cb68f91201d9180a00d5 (cherry picked from commit 653e474)
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hornbill-mps is missing
Configure the eMMC data bus and pin mux for eight-bit operation, and set its CLK, CMD, and data pins to 8 mA drive strength. Tested: Compiled successfully and verified on Arthur Signed-off-by: Rajaganesh Rathinasabapathi <Rajaganesh.Rathinasabapathi@amd.com> Co-authored-by: Cursor <cursoragent@cursor.com> (cherry picked from commit b6ed63c)
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Thanks, added hornbill mps |
| pinctrl_emmc_8ma: emmc_8ma { | ||
| pins = "AC14", "AE15", "AD14", "AE14", "AF14", | ||
| "AB13", "AF13", "AC13", "AD13", "AE13"; | ||
| drive-strength = <2>; |
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I compare ast2700-evb.dts
I see that the drive strength for emmccmd (AE15) and emmcdat ("AD14", "AE14", "AF14", "AB13", "AF13", "AC13", "AD13", "AE13") are <1>
drive strength should be same for emmc CLK/CMD/Data?
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Yeah, the HW team tested the eMMC signals in our DC-SCM card and recommended these values. They can vary between platforms depending on the PCB layout and trace lengths.
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Increase emmc drive strength to 8mA