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1. Verilog_Learning_Codes Verilog_Learning_Codes Public

   A comprehensive collection of Verilog HDL modules. This repository covers fundamentals, combinational and sequential circuits, Finite State Machines (FSMs), and memory architectures, targeting appl…

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2. UART-Design-Verification UART-Design-Verification Public

   A synthesizable UART design with an AMBA APB3 slave interface. Verified using SystemVerilog, Assertions (SVA), and functional coverage.

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3. Arbiter Arbiter Public

   this is repo is to show the results of my Arbiter Minor project

4. Arduino-Smart-Lock Arduino-Smart-Lock Public

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5. AXI4-Design-Verification AXI4-Design-Verification Public

   Synthesizable AXI4 Full Slave Memory Controller and a production-grade UVM 1.2 testbench environment in SystemVerilog. Features 5-channel full-duplex transactions, FIXED/INCR/WRAP bursts, WSTRB byt…

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6. riscv-soc-subsystem riscv-soc-subsystem Public

   A complete System-on-Chip (SoC) built around the PicoRV32 RISC-V processor core, featuring an AXI4-Lite bus, boot ROM, SRAM, and UART peripheral. The project spans bare-metal firmware development, …

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