Cmake rework - #35
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LatencyFIFO::clock() both advances the latency counter and reopens the issue slot, so clocking twice per cycle to get two issues also halved the modeled latency. Use one pipeline per issue slot, each clocked once, matching the existing UnitSFU pattern. Throughput stays at 2 issues/cycle; latency and in-flight capacity are restored. Also widens the DRAM return path, which drained only one 32B sector per cycle and would have bottlenecked the request side. Reported by Haocong Luo (SAFARI, ETH Zurich).
Haydelj
reviewed
Aug 6, 2026
| // number of parallel intersection pipelines. | ||
| // each pipeline is a separate unit that is clocked once per cycle, so windening this changes throughput without changing the modeled latency. | ||
| const static uint NUM_ISECT_PIPLINES = 2; | ||
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Let's make this a config parameter: one for tri pipes, one for node pipes
| //each pipline is a seperate path that is clocked once per cycle, so the width sets throughput without scaling the modeled L2 to controller latency. | ||
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| const static uint NUM_REQ_PIPLINES = 2; | ||
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Same thing; this should be a config parameter.
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| UnitDRAMRamulator::UnitDRAMRamulator(Configuration config) : UnitMainMemoryBase(config.size), | ||
| _request_network(config.num_ports, config.num_controllers * 2, 1 << 13), _return_network(config.num_controllers * 2, config.num_ports), _partition_mask(config.partition_stride) | ||
| _request_network(config.num_ports, config.num_controllers * MemoryController::NUM_REQ_PIPLINES, 1 << 13), |
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We should double-check that 2^13 actually matches the channel stride in the DRAM controller
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This PR aims to refactor the old cmake workflow which was functional but still confusing at times.