[blackwell][draft] sm100: Router GEMM Triton kernel fused_router_gemm.py (#229) - #237
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[blackwell][draft] sm100: Router GEMM Triton kernel fused_router_gemm.py (#229)#237Andrewxu313 wants to merge 2 commits into
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Placeholder commit for draft PR. Implementation tracked in: batchgen-agent-metadata/batchgen_design/blackwell/blackwell-kernel-port-v1.md Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
On Blackwell the WGMMA fused-gate .cu is not built. Provide the router logits GEMM as a pure-Triton kernel and route FusedGateContext through it: - batchgen_kernels/triton/fused_router_gemm.py: router_gemm_bias(hidden, weight, bias) -> logits [N,E] FP32 (FP32 tensor-core accumulation) - triton/__init__.py: export router_gemm_bias - cuda_routing.py: FusedGateContext is sm100-aware — stores weight/bias in Python, warmup() no-op, forward() runs router_gemm_bias + the generic-CUDA gate_topk_softmax (compiled for sm100 in sub-task 2) Verified on B200: logits FP32, max_abs_err ~5e-5 vs float32 reference; FusedGateContext top-k indices match reference. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
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Closes #229. Part of #204 (Blackwell Phase 2).
Summary
New triton/fused_router_gemm.py: BF16->FP32 tl.dot matmul [N,K_dim]x[K_dim,E] + fused BF16 bias. torch.matmul not acceptable (BF16 output, loses FP32 accumulation + inline bias).
Spec
blackwell-kernel-port-v1.md § Sub-task 6