Fix reproducibility issue with recent rosetta versions - #175
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) Fixes #46. The reprotest gate failed bimodally (issue #46): jemalloc's configure, built via tikv-jemalloc-sys inside seismic-reth, probes the build host's virtual-address width (48 vs 57-bit/LA57) and bakes it into LG_VADDR, so a mixed-SKU runner pool yields two possible binaries. Pin LG_VADDR=48 -- safe (Linux never returns >48-bit mappings unless explicitly hinted) and jemalloc's compact-rtree fast path. Document that -C target-cpu=generic is likewise load-bearing for blst's ADX host detection. Instrument CI so the next host-sniffing dependency gets localized instead of guessed at: lscpu in both build jobs (records CPU model and virtual address width), and per-file sha256 listings of the unpacked initrd, diffed by reprotest-compare on mismatch to name the exact divergent files. Also debloat /.cache (Rosetta JIT droppings on Apple Silicon builds), copied from upstream flashbots/flashbots-images#175, so local lima builds can match CI measurements.
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Jul 28, 2026
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There was a Apple Silicon reproducibility regression due to recent rosetta versions leaving files in
/.cache, which this PR fixes by adding that directory to the debloat list.