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Configure GPIOs and related settings as per atria mainboard. Refer to RDC#861905 for schematics BUG=b:519011280 TEST=Build atria and verify it compiles without any error. Change-Id: I8555f14e4b7bdfdbfe783605ec328e92d67e5b6b Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/92994 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS lets SoCs and mainboards mix settings-dependent version bits into the memory-training cache key. That allows deployed systems to force a retrain when UPD-relevant settings change without changing the FSP binary. The common FSP2 path only applied those hooks when the cache key was the FSP-M image revision. Platforms using MRC_CACHE_USING_MRC_VERSION used the MRC version from FSP-M producer data directly, so selecting FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS had no effect there. That is wrong for platforms where a setup option changes memory-training inputs while the FSP/MRC binary stays the same. The old cache can still match and stale training data can be reused. Choose the base cache version first, either the MRC version or the FSP-M image revision, then apply the SoC/mainboard memory-settings version to that base. There is no behaviour change unless a platform selects FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS and returns non-zero version bits. Change-Id: Iebc8cc07d992ae48583c6c762ac9bfae142644d6 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/92570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Star Labs setup can expose a memory_speed option which changes the SPD CBFS entry passed to FSP-M. That changes memory-training inputs without changing the FSP binary or the MRC producer version. Select the common FSP memory-settings version hook once from Star Labs common Kconfig, then return a mainboard version from the boards where that option selects a different SPD source. Alder Lake laptop/tablet variants use the selected speed directly. StarFighter also includes the memory-size strap by returning the final SPD CBFS index. This forces a retrain after changing the setup memory-speed option instead of allowing a stale RW_MRC_CACHE entry to match. Tested on StarFighter MTL with memory_speed=2. Before this change, SMBIOS still reported 6400 MT/s after rebooting. With this change the first boot logged an MRC cache version mismatch and selected SPD index 2; SMBIOS then reported Speed 7500 MT/s and Configured Memory Speed 7467 MT/s. The next boot reused RW_MRC_CACHE normally. Change-Id: I38d16f2b045635b27ad9e41c9cf5ef3988485f05 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/92571 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rather than using .fmd templates, generate fmap.fmd directly from the Makefile via printf, using the predefined BIOS sub-regions which are selected for the build. The existing .fmd templates are dropped. For x86 boards with an IFD, ifdtool -F now writes a complete fmap (fmap-ifd.fmd, containing all regions from the descriptor, prefixed with SI_). The build replaces the SI_BIOS line with the generated BIOS region and the usual children (MRC cache, SMMSTORE, VPD, FMAP, COREBOOT), which is top-aligned to the end of the flash. It also replaces the flash size with $(FMAP_FLASH_SIZE), to mitigate any potential issues if the IFD-generated value is not correct (and to be consistent with the other FMAP generation paths). 'ifdtool -F' is now useful on its own: it emits a full FLASH layout derived from the IFD without Makefile placeholders, including the flash size. For x86 boards without an IFD, fmap.fmd is generated directly by the Makefile, containing only the BIOS region and its (optional) children. Similarly for non-x86 boards, fmap.fmd is generated directly using the default non-x86 layout with optional children. Apply strip_quotes to VPD_FMAP_NAME and SPD_CACHE_FMAP_NAME when building the default FMAP entries, since no longer handled by sed substitution. For x86, move the CONSOLE region after VPD, and align to 4k. This ensures optimal packing of the regions / maximum space available for the COREBOOT CBFS. Drop FMAP_CBFS_SIZE for both x86 and non-x86, as it's unnecessary - the COREBOOT CBFS region will extend to the end of the available space in the BIOS container/region. TEST= - build: google/sarien with and without an included ifd.bin - build: emulation/qemu-riscv - run: ifdtool -p <chipset> -F /tmp/layout.fmd <ifd.bin> Change-Id: Id71bad35d9b1012574912c4da431189df799c566 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/92862 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A handful of boards need a FMAP region larger than 512 bytes due to having complex IFD layouts. Since the area after the FMAP is unused due to alignment anyway, bump the size to 0x1000 to match the alignment of the COREBOOT CBFS that follows, ensuring we will have plenty of space available. TEST=build google/sarien with included IFD.bin Change-Id: I5ae55763445d0b207f10a2a27917dbec465303e8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/92871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Drop the fixed default flashmap and use an auto-generated one instead. This allows for a more accurate, and dynamically generated flashmap to be used. Hook up chromeos.fmd in Kconfig instead of default.fmd and reverse the conditional logic, so the correct FMAP is used for ChromeOS builds. TEST=build/boot google/sarien with SPI FLASH CONSOLE enabled Change-Id: I9d6de9674026a30ab7dfb35978b12cde8733ec81 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/92752 Reviewed-by: Alicja Michalska <ahplka19@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the standard Intel iGPU HDA verbs for HDMI/DP audio output for Cannonlake platform. Addresses cbmem log error: > azalia_audio: initializing codec #2... > azalia_audio: - vendor/device id: 0x8086280b > azalia_audio: - no verb! TEST=build/boot google/sarien, verify codec #2 initialized properly. Change-Id: Ib5835a451fcc9ba49457458af81e825df0512e47 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/92779 Reviewed-by: Alicja Michalska <ahplka19@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add cpu_replacement_check to the SoC chip config as the inverse of the UPD (SkipCpuReplacementCheck), so that the UPD default is enabled. This follows the pattern used on Alderlake and newer platforms. Setting this UPD to enabled eliminates an unnecessary cold boot delay due to re-training memory on devices without an internal battery (e.g., Chromeboxes and mini-PCs like the Purism Librem Mini v2). TEST=build/boot google/puff and purism/librem mini v2. Verify that cold boot times decreased by ~10s and FSP-M only takes ~41ms to run. Change-Id: I1de0d92d7bb9603525be1c185b761f26fcfd8ea1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/93152 Reviewed-by: Alicja Michalska <ahplka19@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Jasperlake is a soldered, not socketed SoC; CPU replacement is not possible. Instead of exposing the SkipCpuReplacementCheck UPD and having all boards select it, simply set it to 1/true at the SoC level and drop the board-facing config. As all JSL boards in tree already set the UPD, this is a no-op. Change-Id: I76c53e497a7dd8b612c81d7cd14a8b922c32158f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/93153 Reviewed-by: Alicja Michalska <ahplka19@gmail.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add a compatibility macro in compiler.h so it maps to the standard 'typeof'. This prepares the codebase for the migration to -std=gnu23 without breaking compatibility with C11/C17. Change-Id: If3b72881c0d45918e6fd279a6edb21c31cc5775e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/93119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Configure the PMC GPE0_DW2 mapping to GPP_C to align GPIO event routing with the board pad configuration.This enables GPP_C-based GPIO events to be delivered through the expected GPE mapping for platform wake/event handling. Change-Id: Iea4dae48696b513333cb6391f704c248ade4db09 Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/93194 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This file uses `uint8_t`, which is defined in `stdint.h`, so include said header. Note that this would not cause build errors if files that include `soc_info.h` have already included `stdint.h` earlier. Change-Id: I3f85d641a4654f2da0f8f7b7abb1bbf22f9745e1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/93117 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
To meet the panel specification, TS_POWER must be enabled after the backlight. Removing the GPIO definition from the firmware ensures the power sequence is handled correctly by the kernel. BUG=b:496733821 TEST=Verify TS functionality on Google/Quartz. Change-Id: I608575397ffb8ec5dc940de229c24b5874e4a88c Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/93210 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
…FSP-S UPDs Provide devicetree control over PCIe link equalization behavior, allowing the use of fixed presets/coefficient values instead of the default hardware-driven equalization presets/coefficient search in phase3 of PCIe gen3 link equalization process. This enables fine-grained tuning and improves reproducibility for platform-specific configurations with a fixed board topology (device down). Note: Phase 2 equalization parameters PcieEqLocalTransmitterOverrideEnable and PcieEqPh2LocalTransmitterOverridePreset are currently not supported by FSP and are therefore not implemented. The following options can be adjusted. PcieEqOverrideDefault: - PCIe override default settings for EQ - Enable/Disable PcieEqMethod: - Choose PCIe EQ method - 0: HardwareEq; 1: FixedEq PcieEqMode: - Choose PCIe EQ mode - 0: PresetEq; 1: CoefficientEq PcieEqPh3NumberOfPresetsOrCoefficients: - Select number of presets or coefficients depending on the mode - Valid range: 0 ~ 11 PcieEqPh3PreCursorList[0..9]: - List of pre-cursor coefficients to be used during phase 3 EQ - Valid range: 0x0 ~ 0x3F PcieEqPh3PostCursorList[0..9]: - List of post-cursor coefficients to be used during phase 3 EQ - Valid range: 0x0 ~ 0x3F PcieEqPh3PresetList[0..10]: - Provide a list of presets to be used during phase 3 EQ - Valid range: 0x0 ~ 0x3F PcieEqPh1DownstreamPortTransmitterPreset: - Allows to select the downstream port preset value that will be used during phase 1 of equalization - Valid range: 0 ~ 0xFFFFFFFF PcieEqPh1UpstreamPortTransmitterPreset: - Allows to select the upstream port preset value that will be used during phase 1 of equalization - Valid range: 0 ~ 0xFFFFFFFF Change-Id: I5470c135302cb0f2435f03f6c390d0e6f13ae70a Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/93266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
There is a PCIe device used on this board that needs to run with 8GT/s (Gen3). Measurements have shown that the PCIe equalization values set by standard hardware link training are not optimal and vary at different boots. This patch therefore uses the fixed equalization method and applies the optimal preset and coefficient values for transmitter signal of the upstream port. BUG=none TEST=Eye RX mask test for PCIe RP #5 (upstream port) passed using an oscilloscope Change-Id: Id6b45f13b4554fdeff932b615fef8df7e6f5cb80 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/93267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
In upcoming patches, mainboard specific adjustments are required before executing FSP-S. Change-Id: I414e23d809d6794da52bd5cc4fd7db25c21e9793 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/93268 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Several effectively empty files were added after commit cf4722d ("src/mb: Update unlicensable files with the CC-PDDC SPDX ID") and thus still carry a regular license. They contain no licensable material (only an SPDX identifier), so dedicate them to the public domain like the other empty stubs. Change-Id: Icd959af689575b6d3897e32e4442248df3b0af56 Signed-off-by: Abdelkader Boudih <coreboot@seuros.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas <nic.c3.14@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
All chipset devices default to "off" in the bd82x6x and sandybridge chipset devicetrees, so explicitly disabling them in the mainboard devicetree is redundant. Reported-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Abdelkader Boudih <coreboot@seuros.com> Change-Id: I9ad2d2ffe29a160938769c96faba6d415d4bd6a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/93275 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Compress the FSP-M with Zstd to reduce the boottime. Even
though FSP-M and the decompressor is bigger and needs more time
to be loaded from SPI flash it boots faster.
TEST=AMD/jaguar boots 18msec faster.
FSP-M size LZMA: 177431
FSP-M size Zstd: 188129
6% increase in file size.
Change-Id: I4ca6bc21b56b3d1e78f94551ca1152ef1a076423
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/92900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Inline the DRAM parameter default configuration and header setup directly into `dram_run_full_calibration`, and remove the now unused `initialize_dramc_param` and `mem_init_set_default_config` APIs. Specifically: - Moving the configuration setup into `dram_run_full_calibration` makes it self-contained and avoids exposing setup details to `mt_mem_init_run`. - Inlining the header version and size initialization directly into the setup flow. - Removing `initialize_dramc_param` fixes a bug where `header.config` was being wiped out by `memset` inside `initialize_dramc_param` right before full calibration. - Removing the single-use `mem_init_set_default_config` helper simplifies the memory initialization flow. BUG=none TEST=emerge-rauru coreboot BRANCH=none Change-Id: I632606ed9f909d278da7db334a518da8303c8427 Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/93273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
When memory configurations (such as scrambling or DVFS) change, the system might still attempt to perform fast calibration using incompatible cached data from flash because the configuration in the cache was not being validated. This patch introduces a generic validation mechanism: - Centralizes coreboot-controlled configuration flags in a new helper `get_expected_config()`. - Validates the cached `header.config` against `get_expected_config()` in `dram_run_fast_calibration()`, masking out the run-time `FAST_K` flag. - Triggers a full re-calibration if a mismatch is detected. - Synthesizes the `DRAMC_CONFIG_DVFS` bit from the old `config_dvfs` cache field at run-time to maintain backward compatibility with older caches. - Logs config mismatch as INFO instead of ERROR/WARNING to avoid misleading warnings when configuration changes are intended. - Cleans up `get_dram_geometry_str` and `get_dram_type_str` by making them `static`. BUG=none TEST=emerge-rauru coreboot BRANCH=none Change-Id: Ic9747b25e5ea2cb1b9354fb521d03055e4fab5a3 Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/93274 Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
Tests on AMD phoenix show that system boots when ISH A and ISH B is present in the directory tree and it even boots from ISH B when ISH A was corrupted. It's unclear what B:285390041 is about and why it didn't work back then. Commit d7eddbf ("mb/google/myst: Remove deprecated board") removed the only mainboard that was affected, thus also drop the workaround. Change-Id: I95c9b90bf3ceae1b53de586d49cb1ac136c6fdff Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/93178 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Include default ACPI brightness levels in fatcat DSDT to provide XBCL and prevent below error message at boot. kernel error message: [ 21.200643] ACPI: video: [Firmware Bug]: ACPI(GFX0) defines _DOD but not _DOS [ 21.210018] ACPI: video: Video Device [GFX0] (multi-head: yes rom: no post: no) [ 21.219785] ACPI BIOS Error (bug): Could not resolve symbol [^^XBCL], AE_NOT_FOUND (20250807/psargs-332) [ 21.231832] ACPI Error: Aborting method \_SB.PCI0.GFX0.LCD0._BCL due to previous error (AE_NOT_FOUND) (20250807/psparse-531) Change-Id: I87e9da9248dfb6aee776c21d5168a2761c7b4914 Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/93021 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id 47eedac625ea: 2026-05-11 17:28:53 +0800 - (This FSP is aligned to BIOS ID 3038.P27 PLR5 release.) to commit id ca4f8b702db0: 2026-05-26 11:30:47 +0800 - (Edge Platforms ARL-UH IPU 2026.3 (6114_54) FSP) This brings in 9 new commits: ca4f8b702db0 Edge Platforms ARL-UH IPU 2026.3 (6114_54) FSP 89292eff0437 Edge Platforms MTL-UH IPU 2026.3 (6114_54) FSP 9c3f006088a6 Edge Platforms ADL-PS IPU 2026.3 (7116_51) FSP a51764dbfadf Edge Platforms ADL-S IPU 2026.3 (7116_51) FSP 969a37e1a1c7 Edge Platforms ADL-P IPU 2026.3 (7116_51) FSP 6e1ee3feef69 Edge Platforms RPL-PS IPU 2026.3 (7116_51) FSP 2a9953f6682c Edge Platforms RPL-P IPU 2026.3 (7116_51) FSP 8de0c2d059e2 Merge branch 'master' of https://github.com/intel/FSP dc6831b944bb IPU2026.3 - New FSP UPDs for NTB Support. Change-Id: I9f8af3e64a55a5028a511c8021da38369c0074f5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/93042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Make the directory layouts more consistent. Change-Id: Iccd60642308459d5e86b3c020e9d3a563f162d4a Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/93199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
GPIO table that was generated with intelp2m caused some issues with functionality like HDMI HPD. Replace the GPIO table with one written by hand using Intel's documentation as a reference (#743330-001). Change-Id: Ie1f6a1a9e3ef5049b342a8f04b795a9200c55a17 Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/92369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The `uart_input_clock_divider()` function returns 16 unless it is overridden, which this SoC does not do. So, replace this magic 16 value with a function call. This is consistent with all the other uses of `uart_baudrate_divisor()` in the tree. Change-Id: I95fd8bae645d6e80cfd2bf9c3f6d46b1e9e79cff Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/93257 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Every `uart_baudrate_divisor()` call in the tree takes the same three parameters (the results of calling three functions). Make things less verbose by introducing `uart_get_baudrate_divisor(), which takes zero parameters. To prevent confusion, rename `uart_baudrate_divisor()` to `uart_calc_baudrate_divisor()`; it is kept around in case one desires to calculate the divisor using other values. Move the declaration of `uart_input_clock_divider()` up a bit so that it can be used in `uart_get_baudrate_divisor()`, which is placed just below `uart_calc_baudrate_divisor()`. Change-Id: I5de319de5c2e551ac5acd3061897d6d3cc07f36a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/93258 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use MEMORY_TYPE_DDR4 needs <smbios.h>. Change-Id: I0db785ab453fa3cd3d52d2b133647e2ca762801d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/93227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Change-Id: I9fdd485e164757f5b019dfe0d8bb3e1dcef85f16 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/93072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Replace the numbers in hda_verb.c with human-readable descriptions. The new format was obtained by running hda-decoder. Change-Id: If4cc14efc4e404e2c80d1ce2725edfd72cbf78d7 Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/93549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nicholas <nic.c3.14@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Probe FW_CONFIG for STORAGE_TYPE and configure the storage power sequencing gpios accordingly. Also enable the storage devices in device tree based on FW_CONFIG. BUG=None TEST=Build Atria BIOS image and boot to OS in both unprovisioned and provisioned FW_CONFIG scenarios. Change-Id: I731442b7be571fe4394f3c3095e213861581f932 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/93384 Reviewed-by: Huang, Cliff <cliff.huang@intel.com> Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some FW_CONFIG options are renamed to improve the clarity of their use-case. Update the FW_CONFIG/UFSC definitions accordingly. BUG=None TEST=Build Atria BIOS image and boot to OS. Change-Id: Ifab57d68725c17bf59a3f5cf1e3f9ccf109ec3ae Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/93561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com> Reviewed-by: Pranava Y N <pranavayn@google.com>
BUG=b:522870994 TEST=Build BIOS image and boot to OS in atria. Change-Id: I8fca059417bcb87744fced31dcb9314e3fc8eaf1 CoAuthored-by: Zhixing Ma <zhixing.ma@intel.com> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/93287 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, keyboard backlight support is statically defined in a mainboard's devicetree. If a user installs a non-backlit keyboard in a supported model, the OS will still expose backlight controls via ACPI. The EC provides a hardware detection bit for the keyboard type. Bit 6 (at offset 0x34) is set if a backlit keyboard is physically connected. This register behaviour was observed across multiple generations with different keyboards. (e.g. X230, T440p, T450s) Research notes: https://github.com/froonix/ec-research/wiki/ThinkLight-vs.-Keyboard-Backlight Furthermore, respect the existing option 'backlight' and disable keyboard backlight if this device is disabled by user choice. TEST=Tested on X230/T440p with different keyboards, works as expected. Change-Id: I685df62ec488a693262addb966ec93f71df2f8bb Signed-off-by: Christian Schrötter <cs@fnx.li> Reviewed-on: https://review.coreboot.org/c/coreboot/+/92929 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As a follow-up to the addition of the Realtek ALC1150 to include/device/azalia_codec/realtek.h, replace the numeric pin widget node IDs in hda_verb.c with human-readable descriptions. All changes were tested by building timeless ROMs and comparing the hashes. Change-Id: Id88ef543bee1f766c4f20c221ad748548c398bf3 Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/93601 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nicholas <nic.c3.14@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Add enums for the pin widget node IDs for Realtek ALC662, ALC892 and ALC1200. The values are taken from the respective datasheets. Change-Id: I2e6b5bcae9d7884f8ce088a88699f152bf9b507f Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/93608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nicholas <nic.c3.14@gmail.com> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Birman+ supports the fTPM emulated by PSP. This also enables build testing the fTPM code. This adds the following new log messages: [DEBUG] PSP: Querying PSP capabilities...OK [DEBUG] PSP: Querying fTPM capabilities... OK [DEBUG] PSP: Querying fTPM capabilities... OK [DEBUG] TPM: CRB buffer created at 0x7b5ee000 [SPEW ] fTPM: CRB TPM initialized successfully [INFO ] Initialized TPM device fTPM ... [DEBUG] PSP: Querying fTPM capabilities... OK [DEBUG] TPM2 log created at 0x7b5b1000 [DEBUG] PSP: Querying fTPM capabilities... OK [DEBUG] ACPI: * TPM2 [DEBUG] ACPI: added table 4/32, length now 68 Change-Id: Ic99a7c460944985b57324e245724082dfeae9391 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89439 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Speed up accessing the SPI flash a bit by using Quad IO 1-4-4 mode. TEST=Can still boot on AMD/birman+. Change-Id: I0f62c010600ea54c32b90d0dc670d4702b806aad Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/93521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
All other System76 boards configure bootblock GPIOs early, so update oryp6 and tgl-h to match. Change-Id: Iafdbdcaaf4a70494c81a9e24cea3aa849da2cdec Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/93564 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
galp5 has an extra include file for dGPU GPIOs that has gone unused because the driver is not merged. Drop it from the tree so it can be changed as needed in the changeset that enables the driver. Change-Id: I38ec8180fc1d8f2e580b5f8c9ed7e82bab549add Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/93563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Drop the first IO decode range to match the other CNL boards. Change-Id: I5303375db5930e7974e040790b83f74a82aff6c5 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/93534 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change-Id: Ic30bec272e82535f6f606033c3ba512662cb2c8b Signed-off-by: Jeremy Soller <jackpot51@gmail.com>
crawfxrd
marked this pull request as ready for review
July 13, 2026 19:37
These values were taken from Alder Lake. Change-Id: I53c6a20a3d912fe2f2eee4e05de50478b6473199 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com>
The newer batch of these boards do not de-assert VW PLTRST# on S3 resume, causing the units to not power on in the EC code. Switch them to S0ix as a workaround. Enable CSME in CMOS options by default so that S0ix will work. Change-Id: I95337c1391102db9e020e82bdd938659c1a4f905 Signed-off-by: Tim Crawford <tcrawford@system76.com>
The Infineon SLB 9672 on newer Clevo machines regularly fails TPM Resume on S3 with the error `TPM_RC_VALUE`. Per TPM2 spec, handle the failure by performing a TPM Restart. > The startup behavior defined by this specification is different than > TPM 1.2 with respect to Startup(STATE). A TPM 1.2 device will enter > Failure Mode if no state is available when the TPM receives > Startup(STATE). This is not the case in this specification. It is up > to the CRTM to take corrective action if it the TPM returns > TPM_RC_VALUE in response to Startup(STATE). Fixes the following error from being repeatedly logged in Linux: > kernel: tpm tpm0: A TPM error (256) occurred attempting get random Ref: Trusted Platform Module Library, Part 1: Architecture, rev 1.59 Change-Id: I3388007d4448c93bd0dda591c8ca7d1a8dc5306b Signed-off-by: Tim Crawford <tcrawford@system76.com>
Apply commit 8851b5b ("soc/intel/pantherlake: Program HDA SVID/SSID") to Meteor Lake. Intel introduced a new UPD specifically for setting the HDA subsystem ID in FSP-M. Using SiSsidTablePtr in FSP-S no longer works as it will be locked with a default value of 0 by that point. Tested on Clevo V560TU with MTL FSP 4122.12 (0D.00.A8.20). TEST=PCI config space for HDA device has subsystem ID set. Change-Id: I5e668747d99b955b0a3946524c5918d328b8e1d3 Signed-off-by: Tim Crawford <tcrawford@system76.com>
The Bonobo has 2 AMPs: one for the speakers and one for the subwoofer. Smart AMP data was collected using a logic analyzer connected to the IC during system start on proprietary firmware. This data is then used to generate a C file [1]. [1]: https://github.com/system76/smart-amp Change-Id: I5389a9890563ebd3adb20096b6225f474bc006f9 Signed-off-by: Tim Crawford <tcrawford@system76.com>
The Meerkat 9 is an Intel Meteor Lake-H based small form factor desktop computer based on the Asus NUC-155H R2. Change-Id: I37a0b808cf383379b8e284831644c824c0d4817e Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com>
System76 EC supports a lock bit on Clevo-based boards (`ME_WE`) that prevents writing its flash when enabled. Extend this lock to system flash by protecting regions when the `SECURITY` feature is present and enabled. Change-Id: Ifd5f77e8516bfd538409a079022f444a571d4e72 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: I4b07846c404eb93ab4baf0a78a4bbffcc5d8afca Signed-off-by: Tim Crawford <tcrawford@system76.com>
Add a driver for laptops with NVIDIA Optimus (hybrid) graphics. The driver provides ACPI support for dynamically powering on and off the GPU, NVIDIA Dynamic Boost support, and a function for enabling the GPU power in romstage. References: - DG-09845-001: NVIDIA GN20/QN20 Hardware Design Guide - DG-09954-001: NVIDIA GN20/QN20 Software Design Guide Change-Id: I2dec7aa2c8db7994f78a7cc1220502676e248465 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: I4ca91ff631dd4badbfba72e69651f03753323a54 Signed-off-by: Tim Crawford <tcrawford@system76.com>
The GPU sometimes crashes when GPU Boost is used. Disable the feature until root cause can be identified and resolved. Change-Id: Ib3624c1241921268627cfc85b4427bc9891fa0a3 Signed-off-by: Tim Crawford <tcrawford@system76.com>
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Update from the 26.03 tag to commit 34c0dc4 ("mb/system76/whl-u: Use genx_dec of other CNL boards").
This is 21 commits ahead of the 26.06 tag, as it includes some upstreamed maintenance commits for our boards.
Current branch is preserved as
system76-26.03.Commits not upstreamed
Notes